The present invention is related to the invention described in co-pending U.S. patent application Ser. No. 10/082,050, filed Feb. 14, 2002 in the name of inventors Stephen R. Cebenko et al. and entitled xe2x80x9cIntegrated Circuit Base Transistor Structure and Associated Programmable Cell Library,xe2x80x9d and co-pending U.S. patent application Ser. No. 09/400,029, filed Sep. 21, 1999 in the name of inventor John A. Schadt et al. and entitled xe2x80x9cIntegrated Circuit with Standard Cell Logic and Spare Gates,xe2x80x9d both of which are commonly assigned herewith and hereby incorporated by reference herein.
The present invention relates generally to integrated circuits and integrated circuit design processes, and more particularly to techniques for arranging and implementing spare gates in an integrated circuit design.
Standard cell application-specific integrated circuits (ASICs) provide a number of significant advantages over other types of integrated circuits, including more manageable die size, lower piece-part cost, higher performance, and more reliable design flow. The standard cell approach is generally considered preferable to other competing approaches such as custom design and programmable logic. As a result, most existing integrated circuit computer-aided design (CAD) tools, such as place and route tools, are configured for operation with the standard cell approach. Examples of standard cell CAD tools known in the art include the Apollo toolset commercially available from Avanti, and the Silicon Ensemble and First Encounter toolsets commercially available from Cadence Design Systems. In general, CAD tools designed for programmable logic are often incompatible with standard cell tools and may require specially trained experts.
One potential problem associated with the standard cell approach is that non-recurring expense (NRE) and process cycle time for development of a given design may still be unduly high. The principal components of the NRE are the cost of a new lot start and the cost of a new mask set as required to implement changes in a standard cell design. As the transistor technology shrinks in size, the lot start and mask set costs can increase considerably. With regard to process cycle time, ASICs typically undergo several design iterations before qualifying for full production. Reaching production with pure standard cell technology can thus be costly and time consuming at a time when market forces are squeezing costs and shortening development cycles.
A number of techniques have been developed in an attempt to alleviate the above-noted problem of the standard cell approach.
One such technique involves the use of so-called multi-chip shuttles to amortize the lot start and mask set costs over several chips. Basically, a prototype lot is ordered for model production only where there may be four to six individual chips placed on the same wafer and reticle. The drawbacks of this technique include a limited die size for each constituent chip, difficulty in timing and coordination of mask order and other functions across four to six chip projects, and potential saw-apart and packaging problems.
Another known technique involves the embedding of spare standard cell gates in a chip netlist to be used at a later time for design changes. However, these spare gates are generally hand-instantiated into the netlist by the customer, the level of design change supported is extremely limited, and wiring the change into the design can be difficult due to poor cell placement.
A third technique involves embedding programmable logic within a standard cell ASIC. However, as mentioned previously, programmable logic generally requires specialized CAD tools, and thus can create tool interface problems when used in a standard cell ASIC. For example, the use of a gate array place and route tool for a standard cell ASIC will generally require conversion of standard cell tool infrastructure over to the gate array tool and corresponding re-training of standard cell tool users, thereby imposing a high development cost burden on what are typically only a few candidate applications. In addition, the use of programmable logic can create difficult xe2x80x9cfloor planxe2x80x9d issues. Other drawbacks include the fact that programmable gate array density is typically only half to less than half the density of standard cell, which affects die size and thus piece part cost, and can also impact performance.
It is therefore apparent that a need exists for improved techniques for arranging and implementing spare gates in an integrated circuit design, preferably in a manner that is programmable but also fully compatible with standard cell CAD tools.
The present invention solves one or more of the above-noted problems by providing spare gates distributed in xe2x80x9cislandsxe2x80x9d or other types of groups throughout an integrated circuit design prior to or in conjunction with a place and route process, and then converting one or more of the spare gates within the place and route process to active logic gates. The invention in an illustrative embodiment utilizes spare gates that are constructed by replication of a base transistor structure of a programmable cell technology that is fully compatible with standard cell CAD tools.
In accordance with one aspect of the invention, an integrated circuit includes standard cells interspersed with spare gates. The spare gates are arranged in multiple groups of spare gates, with each group of spare gates within a corresponding designated spare gate area of a standard cell portion of the integrated circuit. At least a given one of the groups of spare gates is arranged between first and second rows of the standard cells and includes one or more rows of spare gates, with each row of spare gates including multiple base transistor structures arranged adjacent to one another along longitudinal dimensions of the structures. The spare gates may be converted to active gates in conjunction with the automated place and route process using only conductors in one or more metal layers of the integrated circuit.
In an illustrative embodiment, the multiple groups of spare gates are configured as a plurality of spare gate islands distributed throughout the standard cell portion of the integrated circuit, with one of more of the spare gate islands comprising an mxc3x97n array of spare gate cells arranged between rows of the standard cells, where both m and n are greater than one. Each of at least a subset of the spare gates in the given group preferably comprises a plurality of the base transistor structures. The spare gate islands may be distributed throughout the standard cell portion of the integrated circuit in a substantially uniform manner, for example, in accordance with a predetermined geometric pattern. The spare gate islands may therefore themselves be configured in the form of an array, that is, an array of spare gate islands distributed throughout the standard cell portion of the integrated circuit.
As noted above, the standard cells and spare gates are preferably placed in accordance with a placement operation of an automated place and route process of a standard cell CAD tool, and the spare gates are preferably implemented using a base transistor structure compatible with the standard cell CAD tool. The spare gate areas may be defined using a floorplan operation of the standard cell CAD tool.